The present invention relates to integrated circuit systems and, more particularly, to a method of testing a system-in-package and of a system-in-package whose simplified design is permitted by that method.
The advent of integrated circuits made it possible to fabricate an entire electronic circuit in a single package. Traditionally, such chips were packaged in separate packages, which then were connected together, for example after being mounted together on printed circuit boards, to form complete systems. More recently, in order to reduce the size of electronic systems further, some manufacturers have begun to package several chips, related to several technologies, in the same package. For example, a processor for controlling a cellular telephone could include a central processing unit (CPU), a nonvolatile memory such as a flash memory and a volatile memory such as a SDRAM, each fabricated on its own chip, and all packaged in the same package. Such a system is called a “System-in-Package” (SIP), a “MultiChip Package” (MCP) or a “MultiChip Module” (MCM).
The connection of the package to external electrical and electronic circuits is via the same kind of external connectors as are used with individually packaged chips. Common examples of such external connectors include legs, pins and solder balls. Of course, with more than one chip inside the package, the number of external connectors of a SIP is commensurately larger than the number of external connectors of an individually packaged chip.
A SIP is tested much as an individually packaged chip is tested: by being mounted on a testing board, with testing pins connected to the external connectors of the SIP. Appropriate voltages are supplied to selected external connectors, and the responses of the SIP at the same external connectors or at other external connectors are observed. The disparate nature of the various chips inside a typical SIP creates problems that do not exist in the testing of individually packaged chips. For example; a CPU typically has many external connectors to test, but the time of the test relatively short (several seconds). By contrast, a memory chip typically has a small number of external connectors to test, but the test may take upwards of ten minutes because each bit of the memory chip must be tested by writing to the bit and then reading the bit. In the case of individually packaged chips, relatively few CPUs can be tested simultaneously, but the test time is relatively short. Conversely, many individually packaged memory chips can be tested together, but the test time is relatively long. Nevertheless, the overall throughputs of individually packaged CPUs and individually packaged memory chips under test are similar. Testing a SIP that includes a CPU and one or more memory chips gets the worst of both worlds: the duration of the test is long, to accommodate the memories; but many testing pins must be provided to access for testing, not only the CPU and the memories, but also the internal corrections that constitute the internal interface between the CPU and the memories.
Note that in order to enable the testing of the internal interface, a prior art SIP must include, in addition to the external connectors of the CPU and the memories, additional external connectors to the internal interface. Normally, the memories are tested via these additional external connectors. While the memories are being tested, the CPU is placed in an idle state so as not to interfere with the testing of the memories.
There is thus a widely recognized need for, and it would be highly advantageous to have, a method of testing SIPs that would overcome the disadvantages of presently known methods as described above